1. Field of the Invention
The present invention relates to a transistor to transistor logic (TTL) to complementary metal oxide semiconductor (CMOS) translator, and more particularly to a high speed, low powered BiCMOS TTL to CMOS translator which relies on an internally generated reference voltage and is capable of driving high loads.
2. Background of the Invention
TTL to CMOS translators are used to convert a logical signal within the TFL operating range into the CMOS operating range. TTL to CMOS translators are commonly found at the input buffers of an integrated circuit (IC) which contains CMOS circuitry. The translator converts a logical high TTL input signal into a logical high CMOS signal and a logical low TL input signal into a logical low CMOS signal.
The TTL operation range is typically between 0.0 to 3.0 volts. A signal between 0.0 and 0.8 volts is a logical low and a signal between 2.0 and 3.0 volts is a logical high. CMOS circuits operate between the full range of Vss and Vcc. If Vss=0.0 volts and Vcc=5.0 volts, then a signal between 0.0 and 2.5 volts is a logical low and a signal between 2.5 and 5.0 is a logical high.
Referring to FIG. 1, a TTL to CMOS translator according to the prior art is shown. The TTL to CMOS translator 10 has a first inverter stage 12 including PMOS transistor M14 and NMOS transistor M16 and a second inverter stage 18 including PMOS transistor M20 and NMOS transistor M22. During operation, a TTL input signal is applied to the input node of first inverter stage 12. This first stage 12 inverts the signal and performs the full TTL to CMOS conversion. The potential at node A is at the full CMOS level (either at Vcc or Vss), but is logically opposite to that of the signal applied at the input node. For example, if a logical high TTL signal is applied to the input node, NMOS transistor M16 is turned on. As a result, node A is pulled down to Vss. Transistor M20 of the second inverter stage 18 pulls up the low CMOS level signal to Vcc, thereby completing the TTL to CMOS translation. If a logical low TTL signal is applied at the input, the complement of the above occurs and the output node is pulled down to Vss.
The TTL to CMOS translator of FIG. 1 has a significant power dissipation problem. When a logical high TTL signal (approximately 2.0 volts) is applied to the input node of translator 10, this voltage is below the turn off voltage of PMOS transistor M14 and above the turn off voltage of NMOS transistor M16. It has been found that when both transistors are on, translator 10 dissipates approximately 2.0 mA of current. The use of multiple translation circuits 10 would therefore quickly exceed the total power budget for most chips. It would not be desirable to use the translator circuit 10 for a complex chip such as a microprocessor, which may require one hundred or more TTL to CMOS translator circuits.
Referring to FIG. 2, another TTL to CMOS translator according to the prior art is shown. This translator 30 has an inverting input stage 31 including PMOS transistor M32 and NMOS transistor M33, an intermediate stage 34 including a pair of cross coupled PMOS transistors M35 and M36 and NMOS transistors M37 and M38, and an output stage 38 including PMOS transistor M39 and NMOS transistor M40.
The input stage 31 inverts the input TTL signal and performs the TTL to CMOS conversion. For example, when a low TTL signal is applied to the input, PMOS transistor M32 pulls up node A to Vref. (The potential of Vref is equal to or slightly less than (2.0+Vt), where Vt is the turn on threshold of PMOS transistor M32.) Since node A is high, transistor M37 is turned on and node B.sup.1 is pulled down to Vss. Transistor M36 is then turned on, node B is pulled up to Vcc, causing transistor M35 to turn off. No current can pass through node B.sup.1 since transistor M35 is off. NMOS transistor M38 is turned off by the low TTL input, and, therefore, no current can pass through node B. The output stage 38 then inverts the Vcc potential at node B to Vss to complete the TTL to CMOS conversion. If a logical high TTL signal is applied at the input, the complement of the above occurs and the output node is pulled up to Vcc.
The translator 30 of FIG. 2 has several power saving features. The cross coupled PMOS transistors M35 and M36 prevent any current from being dissipated through the intermediate stage 34, thus reducing the amount of DC power being consumed. The externally generated reference voltage (Vref&lt;2.0+Vt) is supplied to the source of PMOS transistor M32. When a high TTL signal (2.0 volts) is applied to the input node of translator 30, PMOS transistor M32 is turned off because the difference between the gate voltage and Vref is less than the threshold voltage of the transistor. The DC current dissipation through transistor M32 is cut off as a result, effectively reducing the DC power consumption of the circuit. In the prior art, voltage supply Vref is generated by a constant current source such as a band gap reference or by a current mirror (not shown).
The translator 30, however, also has a number of significant problems. In particular, the external band gap reference or current mirror used to create Vref is susceptible to voltage fluctuations due to coupling from nearby alternating current lines. These fluctuations may cause the transistor M32 to inadvertently turn on, thereby leaking current and increasing power consumption. Another disadvantage of translator circuit 30 is its slow switching speed. The Vcc potential at either node B or node B.sup.1 must dissipate before the translator 30 can latch a new TTL input signal. As a result, symmetrical switching characteristics are not obtainable and a recovery time is required after each translation. Yet another disadvantage of the translator circuit is it relies solely on CMOS devices which generally have poor gain characteristics. In order to increase drive capability of the circuit, it is required to fabricate large transistors on the die, which wastes valuable space on the die.